package ChiselSoc

import ChiselSoc.ImemPortIo.WORD_LEN
import chisel3.util.experimental.loadMemoryFromFile
import chisel3._
import chisel3.stage.ChiselStage
import chisel3.util._

//定义memory接口，实际上只有一个地址信号和一个指令信号

class ImemPortIo extends Bundle{
  val addr = Input(UInt(WORD_LEN.W))
  val inst = Output(UInt(WORD_LEN.W))
}

class Memory extends Module {
  val io = IO(new Bundle {
    val imem = new ImemPortIo()
  })

  //实现返回内存的内容
  //定义一个深度为16384，宽度为8的存储器
  val mem = Mem(16384, UInt(8.W))
  loadMemoryFromFile(mem, "C:\\Users\\86130\\Desktop\\chisel_spark\\src\\main\\scala\\ChiselSoc\\fetch.hex")

  //将mem的深度进行拼接

  io.imem.inst := Cat(
    mem(io.imem.addr + 3.U(WORD_LEN.W)),
    mem(io.imem.addr + 2.U(WORD_LEN.W)),
    mem(io.imem.addr + 1.U(WORD_LEN.W)),
    mem(io.imem.addr)
  )

}

object ImemPortIo {
  val WORD_LEN = 32
}

object MemoryMain extends App {
  println("Generating the adder hardware")
  emitVerilog(new Memory(), Array("--target-dir", "generated/ChiselSoc/Memory"))
}